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LTC6907
5
6907fa
–
+
4
6
1
OP AMP
fOSC
150
DRIVER
fOSC
IFB
OUT
6907 BD
3
DIV
PROGRAMMABLE
DIVIDER (n)
(
÷1, ÷3, ÷10)
THREE-LEVEL
INPUT
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
(MASTER OSCILLATOR)
SET
V+
2
GND
VSET VGRD 650mV
ISET = IFB
FREQUENCY-TO-CURRENT
CONVERTERS
BUFFER
GRD
RSET
5M
DIVIDER
SELECT
V+
VSET
5
fOSC = 4MHz
50k
RSET
UU
U
PI FU CTIO S
OUT (Pin 1): Oscillator Output. The OUT pin swings from
GND to V+ with an output resistance of approximately
150
. For micropower operation, the load resistance
must be kept as high as possible and the load capacitance
as low as possible.
GND (Pin 2): Ground.
DIV (Pin 3): Divider Setting Input. This three-level input
selects one of three internal digital divider settings, deter-
mining the value of N in the frequency equation. Tie to GND
for
÷1, leave floating for ÷3 and tie to V+ for ÷10. When left
floating, the LTC6907 pulls Pin 3 to mid-supply with a
2.5M resistor. When Pin 3 is floating, care should be taken
to reduce coupling from the OUT pin and its trace to Pin 3.
Coupling can be reduced by increasing the physical space
between traces or by shielding the DIV pin with grounded
metal.
SET (Pin 4): Frequency Setting Resistor Input. Connect a
resistor, RSET, from this pin to GND to set the oscillator
frequency. For best performance use a precision metal or
thin-film resistor of 0.1% or better tolerance and 50ppm/
°C
or better temperature coefficient. For lower accuracy
applications, an inexpensive 1% thick-film resistor may be
used. Limit the capacitance in parallel with RSET to less
than 10pF to reduce jitter and to ensure stability. The
voltage on the SET pin is approximately 650mV at 25
°C
and decreases with temperature by about –2.3mV/
°C.
GRD (Pin 5): Guard Signal. This pin can be used to reduce
PC board leakage across the frequency setting resistor,
RSET. The GRD pin is held within a few millivolts of the SET
pin and shunts leakage current away from the SET pin. To
control leakage, connect a bare copper trace (a trace with
no solder mask) to GRD and loop it around the SET pin and
all PC board metal connected to SET. Careful attention to
board layout and assembly can prevent leakage currents.
The use of a guard ring provides additional shielding of
leakage currents from the SET pin and is optional. If
unused, the GRD pin should be left unconnected.
V+ (Pin 6): Voltage Supply (3V to 3.6V). A 0.1
F
decoupling capacitor should be placed as close as pos-
sible to this pin for best performance.
BLOCK DIAGRA
W
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